The present disclosure describes systems and techniques relating to analog to digital converter (ADC) circuitry, such as pipelined ADC circuitry.
The pipelined ADC has become a popular ADC architecture for sampling rates from a few megasamples per second (Msps) up to 100 Msps or greater. Resolutions generally range from a few bits at the faster sample rates up to 16 bits at lower rates. These resolutions and sampling rates cover a wide range of applications, including charge coupled device (CCD) imaging, ultrasonic medical imaging, digital receivers, base stations, digital video (for example, high definition television, HDTV), digital subscriber, lines (DSL), cable modems, and fast Ethernet.
FIG. 1 illustrates a schematic of prior art pipelined ADC circuitry 100. The circuitry 100 operates in two phases, a sample phase 110 wherein an input voltage (Vin) 125 is provided to the circuit, and a hold phase 120 wherein the input voltage 125 is compared to a number of reference voltages 130 to determine a residual voltage output 135 that is a portion of the input voltage 125.
During the sample phase 110, the input voltage 125 is provided to and stored across a collection of sampling capacitors 140 that are arranged in parallel. A capacitor 145 is reset in sample phase 110. The input voltage 125 is also stored on a feedback capacitor 145, which is also used as a sampling capacitor during the hold phase (e.g., to reduce the amount of area needed for the sampling capacitors).
Referring now to the hold phase 120, the input voltage 125 (now stored by the feedback capacitor 145) is compared by an opamp 150 to a collection of reference voltages applied to the sampling capacitors 140 to determine a residual voltage output 135 that presents an output voltage Vout that is substantially the input voltage 125 with the reference voltage added or subtracted from it.
Bandwidth is determined for a given sampling frequency, and for high accuracy an increased number of sampling capacitors 140 are generally needed. But as the number of sampling capacitors in the circuitry 100 is increased, the feedback factor decreases. One approach to this problem is to implement multiple opamps 150. But as the number of sampling capacitors 140 and opamps 150 increases, so too does the device size as well as the device's power requirements.